The present invention relates to a circuit arrangement for digital filters by which digital input signals occurring in the pure binary code and in two's complement notation during short pulses of a filter sampling signal are processed in serial form, and which contain a parallel-to-serial converter at the input end, at least one adder, at least one shift register used as a status register, at least one multiplier circuit to which an input-data-dependent signal and a factor which is constant at least during the multiplication are applied as the multiplier and the multiplicand, respectively, and a serial-to-parallel converter at the output end.
In a book by S. A. Azizi "Entwurf und Realisierung digitaler Filter", Munich, 1981, it is mentioned on pages 288/89 that digital filter can be realized as circuits (called "hardware realization" there) which process the input signals in serial form, and that the individual subcircuits of the digital filter are then suitable serial arrangements, i.e., serial multipliers, serial adders, etc. It is also stated that this mode of operation requires, in addition to the filter sampling signal, a further sampling signal, referred to as "bit clock" there, whose repetition rate may be much higher than that of the word clock depending on the word length of the output variables and coefficients.